The 74LS73 Dual JK Flip-Flop is a dual negative-edge-triggered J-K flip-flop from Texas Instruments, featuring a master-slave configuration with complementary outputs. This device contains two independent flip-flops, with each flip-flop being triggered on the falling edge of the clock pulse. 74LS73 Dual JK Flip-Flop allow the J and K inputs to change during both the HIGH and LOW phases of the clock without affecting the output, provided the setup and hold times are respected.
Features :
- Propagation Delay Time: 20 ns
- High Level Output Current: – 0.4 mA
- Low Level Output Current: 8 mA
- Number of Channels: 2
- Operating Temperature Range: 0°C to +70°C
Package Includes:
1 x 74LS73 Dual JK Flip-Flop IC